Detector de Padrão Verilog: Detecção Avançada de Sequência em FPGA

Um exemplo anterior explorou um detector de sequência simples. Aqui está outro exemplo para um detector de padrão que detecta um padrão ligeiramente mais longo.

Design

module det_110101 (
    input clk,
    input rstn,
    input in,
    output out
);
    parameter IDLE = 0, S1 = 1, S11 = 2, S110 = 3, S1101 = 4, S11010 = 5, S110101 = 6;
    reg [2:0] cur_state, next_state;

    assign out = cur_state == S110101 ? 1 : 0;

    always @ (posedge clk) begin
        if (!rstn)
            cur_state <= IDLE;
        else
            cur_state <= next_state;
    end

    always @ (cur_state or in) begin
        case (cur_state)
            IDLE : begin
                if (in) next_state = S1;
                else next_state = IDLE;
            end
            S1: begin
                if (in) next_state = S11;
                else next_state = IDLE;
            end
            S11: begin
                if (!in) next_state = S110;
                else next_state = S11;
            end
            S110 : begin
                if (in) next_state = S1101;
                else next_state = IDLE;
            end
            S1101 : begin
                if (!in) next_state = S11010;
                else next_state = IDLE;
            end
            S11010: begin
                if (in) next_state = S110101;
                else next_state = IDLE;
            end
            S110101: begin
                if (in) next_state = S1;
                else next_state = IDLE;
                // Bug 2
            end
        endcase
    end
endmodule

Testbench

module tb;
    reg clk, in, rstn;
    wire out;
    integer l_dly;

    always #10 clk = ~clk;

    det_110101 u0 (
        .clk(clk),
        .rstn(rstn),
        .in(in),
        .out(out)
    );

    initial begin
        clk <= 0;
        rstn <= 0;
        in <= 0;
        repeat (5) @ (posedge clk);
        rstn <= 1;

        @(posedge clk) in <= 1;
        @(posedge clk) in <= 1;
        @(posedge clk) in <= 0;
        @(posedge clk) in <= 1;
        @(posedge clk) in <= 0;
        @(posedge clk) in <= 1;
        @(posedge clk) in <= 1;
        @(posedge clk) in <= 1;
        @(posedge clk) in <= 0;
        @(posedge clk) in <= 1;
        @(posedge clk) in <= 0;
        @(posedge clk) in <= 1;

        #100 $finish;
    end
endmodule

Log de Simulação

ncsim> run
T=10 in=0 out=0
T=30 in=0 out=0
T=50 in=0 out=0
T=70 in=0 out=0
T=90 in=0 out=0
T=110 in=1 out=0
T=130 in=1 out=0
T=150 in=0 out=0
T=170 in=1 out=0
T=190 in=0 out=0
T=210 in=1 out=0
T=230 in=1 out=1
T=250 in=1 out=0
T=270 in=0 out=0
T=290 in=1 out=0
T=310 in=0 out=0
T=330 in=1 out=0
T=350 in=1 out=1
T=370 in=1 out=0
T=390 in=1 out=0
T=410 in=1 out=0
Simulation complete via $finish(1) at time 430 NS + 0